The new method for the design and simulation of a 4-bit accumulator

an accumulator is an adder or subtractor and a register. Sometimes these are combined with a multiplier to form a multiplier–accumulator (MAC). An incremental adds to the input bus, can add this so we can use this function, together with a register, to negate a two‘s complement number. Advanced Silicon (Si), Complementary Metal Oxide Semiconductor (CMOS) manufacturing processes require novel circuit design methodology to achieve high performance. The CMOS process leverages existing 120nm silicon process advancements, but lower device breakdown voltages require new circuits to achieve low voltage operation. These allow for high speed metal oxide semiconductor field effect transistor (MOSFET) technology logic blocks combined with high density and low power CMOS logic. This thesis presents the design of a digital accumulator operating at a 5 Volt supply circuit consuming minimum of power supply. This architecture applies a modified logic family inverter, nand, nor, and xor with 120nm technology circuit.