Chip-Multi Processor (CMP) designs process has been confronted by a number of serious insurmountable technological challenges such as memory wall, memory static power and the limited memory bandwidth as potential bottlenecks of the system performance. To overcome the system performance bottlenecks in future multi-core architectures, emerging memory technologies such as STT-RAM, PCRAM, eDRAM and resistive-RAM due to the many attractive features such: high density, low leakage, and non-volatility are being examined as potential replacements to existent main memories and on-chip caches. In this paper, we propose a novel reconfigurable hybrid cache configuration with hybrid memory technologies, in which STT-RAM, a type of Non- Volatile Memories, is incorporated in the last-level cache with SRAM. This reconfigurable last-level cache consists of a hybrid cache configuration and a run-time reconfiguration mechanism. Based on the read intensity or write intensity of different applications, the reconfiguration mechanism dynamically adapts the last-level cache space during run-time. We accomplish experiments on an 8-core CMP which show that the prop osed architecture achieves an average 77% and 52% energy saving over non-reconfigurable SRAM-only cache and non-reconfigurable hybrid cache architectures.
