Call for Papers : Volume 11, Issue 03, March 2024, Open Access; Impact Factor; Peer Reviewed Journal; Fast Publication

Vedic multiplication techniques for low power floating point multiplier implementation

Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyak bhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in Virtex-5 FPGA and VHDL is used.

Author: 
Dr. Avinash Kumar Yadav
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