Vedic multiplication techniques for low power floating point multiplier implementation

Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyak bhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in Virtex-5 FPGA and VHDL is used.

Author: 
Dr. Avinash Kumar Yadav
Journal Name: 
Int J Inf Res Rev
Volume No: 
03
Issue No: 
05
Year: 
2016
Paper Number: 
1160
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Editorial Board

David Johnson
Jessica Parker
Sarah Conor
John Franklin